Self updating a firmware device

ABSTRACT

The present invention is a method and apparatus to self update a firmware device. A communication interface receives programming information. A parser coupled to the communication interface to parse the programming information into control commands and program data.

BACKGROUND

[0001] 1. Field of the Invention

[0002] This invention relates to microprocessors. In particular, theinvention relates to firmware.

[0003] 2. Description of Related Art

[0004] Non-volatile memories (e.g., flash memories) are increasinglyimportant in many microprocessor applications. One particular use ofnon-volatile memories is in a firmware hub (FWH). A FWH provides anintegrated mechanism to enable security-enhanced platform infrastructurein modern microprocessor platforms. The non-volatile memory in a FWH istypically used for platform code and data storage.

[0005] A flash memory needs to be erased and programmed to store codeand data. Traditional techniques to program flash memories include massprogramming at the manufacturing facility and remote programming withthe aid of the host processor.

[0006] Programming at the manufacturing facility involves the use ofprogramming and test equipment. For applications that require frequentupdates, this programming approach is not practical. Remote programmingby a host processor requires an interface with the host to allow thehost or a special processor to carry out the programming sequence. Inmany applications, the intervention by a host processor is notdesirable. For example, if the flash memory itself is used as a bootdevice from which the host processor obtains the boot code, it isimpossible for the host processor to program its own boot code.

[0007] Therefore, there is a need to have a firmware device having aself-update ability to program itself without an external device.

SUMMARY

[0008] The present invention relates to a method and apparatus to selfupdate a firmware device. The apparatus comprises a communicationinterface to receive programming information and a parser to parse theprogramming information into control commands and program data. Theparser is coupled to the communication interface.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The features and advantages of the present invention will becomeapparent from the following detailed description of the presentinvention in which:

[0010]FIG. 1 is a diagram illustrating a computer system in which oneembodiment of the invention can be practiced.

[0011]FIG. 2 is a diagram illustrating a self-update controlleraccording to one embodiment of the invention.

[0012]FIG. 3 is a diagram illustrating a state diagram of a commandparser according to one embodiment of the invention.

[0013]FIG. 4 is a flowchart illustrating a process to self updateaccording to one embodiment of the invention.

DESCRIPTION

[0014] The present invention is a method and apparatus for self-updatinga firmware device. The update is performed autonomously without theintervention of an external processor. A communication interface circuitreceives the serial data containing the program information. A parserdecodes the program information and generates control commands to acontrol logic circuit. A read buffer stores the program data. Thecontrol logic circuit includes a erase control circuit and a writecontrol circuit. The parser includes a state machine that parses theprogram information and extract program parameters and program data. Thestate machine generates control signals and/or control commands to theerase and write control circuits to erase and write the firmware device.By incorporating the self-update controller to control the firmwaredevice, the technique provides a mechanism to update the firmware devicewithout an external processor.

[0015] In the following description, for purposes of explanation,numerous details are set forth in order to provide a thoroughunderstanding of the present invention. However, it will be apparent toone skilled in the art that these specific details are not required inorder to practice the present invention. In other instances, well knownelectrical structures and circuits are shown in block diagram form inorder not to obscure the present invention.

[0016]FIG. 1 is a diagram illustrating a computer system 100 in whichone embodiment of the invention can be practiced. The computer system100 includes a processor 105, a host bus 110, a host bridge chipset 120,a system memory 130, an audio device 142, a mass storage device 144, anuniversal serial bus (USB) device 146, a super input/output (I/O) device150, a peripheral bus 160, and K peripheral devices 170 ₁ to 170 _(K).

[0017] The processor 105 represents a central processing unit of anytype of architecture, such as complex instruction set computers (CISC),reduced instruction set computers (RISC), very long instruction word(VLIW), explicitly parallel instruction set computing (EPIC), or hybridarchitecture. The invention could be implemented in a multi-processor orsingle processor computer system.

[0018] The host bridge chipset 120 includes a number of interfacecircuits to allow the host processor 105 access to the system memory 130and the peripheral bus 160. The host bridge chipset 120 includes amemory controller 122, a self-update controller 124, a firmware device126, and an I/O controller 128. The memory controller 122 provides aninterface to the system memory 130. The self-update controller 124controls the self updating of the firmware device 126 autonomously,i.e., without the intervention of an external processor such as the hostprocessor. The firmware device 126 is a non-volatile memory to storefirmware such as program and code. In one embodiment, the non-volatilememory is a flash memory. The I/O controller 128 provides control of I/Ofunctions. The I/O controller 128 provides interface to the audio device142, the mass storage device 144, the USB device 146, and the super I/Odevice 150. Other I/O devices may also be controlled by the I/Ocontroller 128.

[0019] The system memory 130 represents one or more mechanisms forstoring information. For example, the system memory 130 may includenon-volatile or volatile memories. Examples of these memories includeflash memory, read only memory (ROM), or random access memory (RAM). Thesystem memory 130 stores a program 132 and a data 134. Of course, thesystem memory 130 preferably contains additional software (not shown),which is not necessary to understanding the invention.

[0020] The audio device 142 includes audio equipment or component suchas speakers, microphones, and other audio peripherals. In oneembodiment, the audio device 142 includes the audio codec AC'97.

[0021] The mass storage device 150 includes CD ROM, floppy diskettes,and hard drives. The mass storage device 150 stores non-volatileinformation such as programs or data. The mass storage device 150provides a mechanism to read machine-readable media. When implemented insoftware, the elements of the present invention are essentially the codesegments to perform the necessary tasks. The program or code segmentscan be stored in a processor readable medium or transmitted by acomputer data signal embodied in a carrier wave, or a signal modulatedby a carrier, over a transmission medium. The “processor readablemedium” may include any medium that can store or transfer information.Examples of the processor readable medium include an electronic circuit,a semiconductor memory device, a ROM, a flash memory, an erasable ROM(EROM), a floppy diskette, a compact disk CD-ROM, an optical disk, ahard disk, a fiber optic medium, a radio frequency (RF) link, etc. Thecomputer data signal may include any signal that can propagate over atransmission medium such as electronic network channels, optical fibers,air, electromagnetic, RF links, etc. The code segments may be downloadedvia computer networks such as the Internet, Intranet, etc.

[0022] The USB device 146 includes devices that are compatible with theUSB standards such as camera, image capture, encoder, decoder, scanner,etc. The super I/O device 150 provides interfaces to a number of I/Ofunctions and devices such as keyboard, mouse, tablet digitizer,track-ball, etc. The super I/O device 150 interfaces to the I/Ocontroller 128 and the self-update controller 124 via a Low Pin Count(LPC) interface bus.

[0023] The peripheral bus 160 provides bus interface to the peripheraldevices 170 ₁ to 170 _(K). In one embodiment, the peripheral bus 160 isthe peripheral component interconnect (PCI) bus. The peripheral devices170 ₁ to 170 _(K) include a network interface device, a modem, a printercontroller, etc.

[0024]FIG. 2 is a diagram illustrating a self-update controller 124according to one embodiment of the invention. The self-update controller124 includes a communication interface 210, a source selector 220, aparser 230, a control logic circuit 240, and a read buffer 250.

[0025] The communication interface 210 provides an interface to a serialdata stream. The serial data may come from a remote device via a modem,or from a test or programming equipment. The serial data contains theprogramming information to update the firmware device. The programminginformation includes the self-update identifier, program parameters, andprogram data. The self-update identifier is a code to inform theself-update controller that the serial data contains the updateinformation. The program parameters include parameters that are neededfor the updating. These parameters may include the block size, thenumber of bytes to be written to the firmware device, the erase blockaddresses, the write block addresses, etc. The program data are theupdate data to be written to the firmware device. The update data mayinclude the boot code in a Basic Input/Output System (BIOS), a specificroutine, a device driver, an exception handler, a set of datastructures, or any other information that needs to be updated.

[0026] The communication interface 210 includes a receiver interface 212and a serial-to-parallel converter 214. The receiver interface 212provides interface function to receive the serial data. Examples ofinterface functions include level translation (e.g., voltage shiftingfrom 12V to 5V), data stripping and error detection. These interfacefunctions may not be needed if the serial data are processed by adedicated communication device such as the legacy serial communicationinterface device. The serial-to-parallel converter 214 converts theserial data stream into parallel data. The parallel data may be of anysize comparable with the parser. Examples of the parallel data sizesinclude four bits, eight bits, or sixteen bits.

[0027] The source selector 220 selects the source for the input to theparser 230. There are essentially two sources: the parallel data fromthe communication interface 210 and the I/O interface data from the LPCbus. The source selector 220 includes a multiplexer controller 222 and amultiplexer 224. The multiplexer 224 is a two-to-one data selector toselect one of the LPC interface data and the parallel data. The LPCinterface data contains information for a normal operation. The paralleldata contains the program information that is used to update thefirmware device. The multiplexer controller 222 controls the selectionof the data. The multiplexer controller 222 receives a reset signal froma system reset circuit and some control signal from the LPC interfacedata. In one embodiment, when the reset signal is activated, themultiplexer controller 222 generates a select signal to the multiplexer224 to select the program information. The multiplexer controller 222has a latching element for the select signal that remains stable duringthe time the parser 230 receives the program information. When theparser completes the update operation, it generates a completion signal(e.g., DONE) to the multiplexer controller 222 so that the select signalcan be reversed forcing the multiplexer 224 to switch to the LPCinterface data for a normal operation.

[0028] The parser 230 decodes the data provided by the multiplexer 224.The parser 230 includes a state machine that generates control commandsto the control logic circuit 240 and the read buffer 250. The statemachine will be described later in FIG. 3.

[0029] The control logic circuit 240 includes an erase control circuit242 and a write control circuit 244. The erase control circuit 242generates signals to erase the firmware device. The write controlcircuit 244 generates signals to program or write the firmware device.

[0030] The read buffer 250 stores the program data received from thecommunication interface 210 and forwarded by the parser 230. The readbuffer 250 is a local memory to buffer the program data which will bewritten to the firmware device under the control of the write controlcircuit 244. The read buffer 250 may be implemented by afirst-in-first-out (FIFO) or a static random access memory (RAM). Thesize of the read buffer 250 is sufficient to store the program data forthe corresponding block in the firmware device.

[0031]FIG. 3 is a diagram illustrating a state diagram 300 of the parser230 shown in FIG. 2 according to one embodiment of the invention. Thestate diagram 300 includes an identification state 310, a programparameters read state 320, a program data buffer state 330, a blockerasure state 340, a block write state 350, a status update state 360,and a normal operation state 370.

[0032] The identification state 310 parses the input data to the parser230 (shown in FIG. 2) and identifies if the data contains a self-updateidentifier. If the data contains the self-update identifier, the statemachine 300 transitions from the identification state 310 to the programparameters state 320. Otherwise, the state machine transitions to thenormal operation state 370.

[0033] In the program parameters read state 320, the state machine 300reads the program information and extract the program parameters basedon a known protocol and/or format. Examples of the program parametersinclude size of program data, erase block addresses, write blockaddresses. In one embodiment, the state machine 300 deposits the eraseblock address in the erase control circuit 242 (in FIG. 2), the writeblock address in the write control circuit 244 (in FIG. 2), and theprogram data size in a terminal count register.

[0034] After the program parameters are obtained, the state machine 300transitions to the program data buffer state 320. In the program databuffer state 320, the state machine 300 stores the program data in thestream of program information received from the source selector 220 (inFIG. 2) to the read buffer 250 (in FIG. 2). If the read buffer 250 is aFIFO, the state machine 300 writes to the FIFO while incrementing a FIFOcounter. When the FIFO counter reaches the maximum count that matchesthe program data size stored in the terminal count register, the storingof the program data is stopped, and the state machine proceeds to theblock erasure state 340.

[0035] In the block erasure state 340, the state machine 300 perform theblock erasure operation. The state machine 300 generates control signalsto the erase control circuit 242 (in FIG. 2) to erase the firmwaredevice at the specified erase block address.

[0036] After the erasure is completed, the state machine 300 transitionsto the block write state 350. In the block write state 350, the statemachines 300 generates control signals to the write control circuit 244(in FIG. 2) to write the data in the read buffer 250 (in FIG. 2) to thefirmware device at the specified write block address.

[0037] After the writing is completed, the state machine 300 transitionsto the status update state 360. In the status update 360, the statemachines 300 updates the status of the update in a status register. Thisstatus register can be later read by an external device such as the hostprocessor 105 (in FIG. 1) or the I/O controller 128 (in FIG. 1). Thestatus may include information about the success of the update, thenumber of bytes to be updated, the specific block addresses for update,or any other relevant information. At the end of the status update state360, the state machine 300 generates a DONE signal to the sourceselector 220 (in FIG. 2) to signal that the update has been completed.

[0038] After the status is updated, the state machine 300 transitions tothe normal operation state 370. In the normal operation state 370, thestate machine 300 receives the LPC interface data and proceeds toperform normal operation. In the normal operation state 370, if thereset signal is activated, the state machine transitions back to theidentification state 310 to prepare for another update if necessary.

[0039]FIG. 4 is a flowchart illustrating a process 400 to self updateaccording to one embodiment of the invention.

[0040] At START, the process 400 reads data provided by the sourceselector 220 (in FIG. 2) (Block 410). Then the process 400 determines ifthe data is a self-update identifier (Block 420). If not, the process400 is terminated. If the data matches the self-update identifier, theprocess 400 reads the program parameters in the next data sequence(Block 430). The program parameters typically include the size of theprogram data and the erase and write block addresses.

[0041] Then the process 400 reads the program data that follows andstores the program data in the read buffer 250 shown in FIG. 2 (Block440). The process 400 determines if all the program data have beenstored in the read buffer (Block 450). If not, the process 400 returnsto block 440 to continue to read and store the program data. If all theprogram data have been stored in the buffer, the process 400 generates ablock erase command to the erase control circuit 242 shown in FIG. 2(Block 460). The process 400 then determines if the erasure has beencompleted (Block 470). If not, the process 400 returns to block 470 towait for the completion of the erasing operation. If the erasure iscompleted, the process 400 generates a write command to the writecontrol circuit 244 shown in FIG. 2 and provides the data from the readbuffer 250 in FIG. 2 (Block 480).

[0042] Next, the process 400 determines if all the program data storedin the read buffer 250 have been written to the firmware device (Block490). If not, the process 400 returns to block 480 to continue theupdate. If all the program data have been written, the process 400 isterminated.

[0043] While this invention has been described with reference toillustrative embodiments, this description is not intended to beconstrued in a limiting sense. Various modifications of the illustrativeembodiments, as well as other embodiments of the invention, which areapparent to persons skilled in the art to which the invention pertainsare deemed to lie within the spirit and scope of the invention.

What is claimed is:
 1. A method to self update a firmware device,comprising: receiving programming information from a communicationinterface; and parsing the programming information into control commandsand program data by a parser.
 2. The method of claim 1 furthercomprising: programming the firmware device based on the controlcommands by a control logic circuit; and storing the program data to bewritten into the firmware device in a buffer.
 3. The method of claim 2further comprising: providing the programming information to the parserby a source selector.
 4. The method of claim 3 wherein providing theprogramming information comprises: selecting one of the programminginformation from the communication interface and an input and output(I/O) channel data by a multiplexer; and controlling a selection of themultiplexer by a multiplexer controller.
 5. The method of claim 2wherein programming the firmware device comprises: erasing the firmwaredevice by an erase control circuit; and writing to the firmware deviceusing the program data in the buffer by a write control circuit.
 6. Themethod of claim 2 wherein the parsing comprises: generating the controlcommands based on the parsed programming information by a state machine,the control commands including at least an erase command and a writecommand.
 7. The method of claim 6 wherein the programming informationincludes at least a self-update identifier, program parameters, and theprogram data.
 8. The method of claim 7 wherein generating the controlcommands comprises: recognizing the self-update identifier; reading theprogram parameters including at least erase and write addresses;generating a buffer write command to write the program data into thebuffer; generating an erase command to the erase control circuit to ablock in the firmware device at the erase address; and generating awrite command to the write control circuit to the program data in thebuffer to the firmware device at the write address.
 9. The method ofclaim 1 wherein receiving comprises: converting serial data into theprogramming information by a serial to parallel converter.
 10. Themethod of claim 5 wherein the I/O data channel is the low pin count(LPC) interface.
 11. An apparatus to self update a firmware device, theapparatus comprising: a communication interface to receive programminginformation; and a parser coupled to the communication interface toparse the programming information into control commands and programdata.
 12. The apparatus of claim 11 further comprising: a control logiccircuit coupled to the parser to program the firmware device based onthe control commands; and a buffer coupled to the parser to store theprogram data to be written into the firmware device.
 13. The apparatusof claim 12 further comprising: a source selector coupled to thecommunication interface and the parser to provide the programminginformation to the parser.
 14. The apparatus of claim 13 wherein thesource selector comprises: a multiplexer to select one of theprogramming information from the communication interface and an inputand output (I/O) channel data; and a multiplexer controller coupled tothe multiplexer to control a selection of the multiplexer.
 15. Theapparatus of claim 12 wherein the control logic circuit comprises: anerase control circuit to erase the firmware device; and a write controlcircuit to write the firmware device using the program data in thebuffer.
 16. The apparatus of claim 12 wherein the parser comprises: astate machine to generate the control commands based on the parsedprogramming information, the control commands including at least anerase command and a write command.
 17. The apparatus of claim 16 whereinthe programming information includes at least a self-update identifier,program parameters, and program data.
 18. The apparatus of claim 17wherein the state machine comprises: a self-update identification stateto recognize the self-update identifier; a program parameters read statecoupled to the self-update identification state to read the programparameters including at least erase and write addresses; a program databuffer state to generate a buffer write command to write the programdata into the buffer; a block erasure state to generate the erasecommand, the erase command causing the erase control circuit to erase ablock in the firmware device at the erase address; and a block writestate to generate the write command, the write command causing the writecontrol circuit to write the program data in the buffer to the firmwaredevice at the write address.
 19. The apparatus of claim 15 wherein thecommunication interface includes a serial to parallel converter toconvert serial data into the programming information.
 20. The apparatusof claim 15 wherein the I/O data channel is the low pin count (LPC)interface.
 21. A system comprising: a host processor; a firmware device;and a self-update firmware controller coupled to the firmware device toself update the firmware device, the controller comprising: acommunication interface to receive programming information, and a parsercoupled to the communication interface to parse the programminginformation into control commands and program data.
 22. The system ofclaim 21 wherein the controller further comprising: a control logiccircuit coupled to the parser to program the firmware device based onthe control commands; and a buffer coupled to the parser to store theprogram data to be written into the firmware device.
 23. The system ofclaim 22 wherein the controller further comprising: a source selectorcoupled to the communication interface and the parser to provide theprogramming information to the parser.
 24. The system of claim 23wherein the source selector comprises: a multiplexer to select one ofthe programming information from the communication interface and aninput and output (I/O) channel data; and a multiplexer controllercoupled to the multiplexer to control a selection of the multiplexer.25. The system of claim 22 wherein the control logic circuit comprises:an erase control circuit to erase the firmware device; and a writecontrol circuit to write the firmware device using the program data inthe buffer.
 26. The system of claim 22 wherein the parser comprises: astate machine to generate the control commands based on the parsedprogramming information, the control commands including at least anerase command and a write command.
 27. The system of claim 26 whereinthe programming information includes at least a self-update identifier,program parameters, and program data.
 28. The system of claim 27 whereinthe state machine comprises: a self-update identification state torecognize the self-update identifier; a program parameters read statecoupled to the self-update identification state to read the programparameters including at least erase and write addresses; a program databuffer state to generate a buffer write command to write the programdata into the buffer; a block erasure state to generate the erasecommand, the erase command causing the erase control circuit to erase ablock in the firmware device at the erase address; and a block writestate to generate the write command, the write command causing the writecontrol circuit to write the program data in the buffer to the firmwaredevice at the write address.
 29. The system of claim 25 wherein thecommunication interface includes a serial to parallel converter toconvert serial data into the programming information.
 30. The system ofclaim 15 wherein the I/O data channel is the low pin count (LPC)interface.